1. Field
Exemplary embodiments of the present invention relate to a memory device and a data input/output method thereof, and more particularly, to technology for increasing the efficiency and stability of a repair operation of a memory device, which is performed during data input/output.
2. Description of the Related Art
During a fabrication process of a semiconductor memory device, any one of a great number of memory cells may become defective. If the semiconductor memory device is discarded as a defective product due to some defective cells, it is inefficient in terms of yield.
Therefore, a defective unit cell is replaced with a redundant unit cell which is additionally installed in a memory device. Accordingly, the entire memory device is recovered to thereby increase the yield.
FIG. 1 is a diagram illustrating a repair operation in a conventional memory device.
The memory device includes a first main memory array 10, a first main page buffer array 20, a first redundancy memory array 15, a first redundancy page buffer array 25, a second main memory array 30, a second main page buffer array 40, a second redundancy memory array 35, and a second redundancy page buffer array 45.
The first main page buffer array 20 is configured to access data of the first main memory array 10. The first main page buffer array 20 performs a program operation of storing data in the first main memory array 10 and a read operation of reading data from the first main memory array 10.
The first redundancy memory array 15 is configured to replace columns including defective memory cells, among a plurality of columns forming the first main memory array 10, by the column as the unit.
The first redundancy page buffer array 25 is configured to access data of the first redundancy memory array 15. The first redundancy page buffer array 25 performs a program operation of storing data in the first redundancy memory array 15 and a read operation of reading data from the first redundancy memory array 15.
The second main page buffer array 40 is configured to access data of the second main memory array 30. The second main page buffer array 40 performs a program operation of storing data in the second main memory array 30 and a read operation of reading data from the second main memory array 30.
The second redundancy memory array 35 is configured to replace columns including defective memory cells, among a plurality of columns forming the second main memory array 30, by the column as the unit.
The second redundancy page buffer array 45 is configured to access data of the second redundancy memory array 35. The second redundancy page buffer array 45 performs a program operation of storing data in the second redundancy memory array 35 and a read operation of reading data from the second redundancy memory array 35.
When an inputted column address corresponds to a defective column among the columns forming the first main memory array 10, the first redundancy page buffer array 25 performs a read/program operation on a column of the columns within the first redundancy memory array 15, instead of the defective column within the first main memory array 10. Similarly, when the inputted column address corresponds to a defective column among the columns forming the second main memory array 30, the second redundancy page buffer array 45 performs a read/program operation on a column of the columns within the second redundancy memory array 35, instead of the defective column within the second main memory array 30.
As illustrated in FIG. 1, the conventional memory device separately includes the first redundancy memory array 15 for replacing defective columns within the first main memory array 10 and the second redundancy memory array 35 for replacing defective columns within the second main memory array 30. Therefore, the defective column within the first main memory array 10 may not be replaced with a column of the second redundancy memory array 35, and the defective column within the second main memory array 30 may not be replaced with a column of the first redundancy memory array 15. Accordingly, when a large number of defective cells exist in any one of the first and second main memory arrays 10 and 30, for example, when such a large number of defective cells as not to be replaced with the first redundancy memory array 15 exist in the first main memory array 10, the entire memory device is to be discarded even though the second redundancy memory array 35 includes columns to replace defective columns.